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Network Wizard for VHDL Test Benches
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Processes | |
| p_source | ( aclk ) |
Procedures | |
| data( signal pkt: in t_slv_arr signal tdata: out std_logic_vector signal tkeep: out std_logic_vector signal tstrb: out std_logic_vector signal tlast: out std_logic signal tvalid: out std_logic variable v_cnt: inout natural variable v_start: in natural variable v_end: in natural ) | |
Types | |
| t_fsm | ( IDLE , TX , LAST ) |
Signals | |
| fsm | t_fsm |