Network Wizard for VHDL Test Benches
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AXI-Stream source

The AXI-Stream source module will send a packet on the bus when pkt_valid is asserted. The done signal is asserted when the transmission is complete. The width of the data bus is defined by a generic.

Instantiation template

i_axis_source : entity nw_util.axis_source
generic map (
GC_BYTES => 4
)
port map (
aclk => aclk,
aresetn => aresetn,
tready => tready,
tvalid => tvalid,
tdata => tdata,
tkeep => tkeep,
tstrb => tstrb,
tlast => tlast,
done => done,
pkt_len => pkt_len,
pkt_valid => pkt_valid,
pkt => pkt
);
Definition nw_axis_source.vhd:73
out tkeep std_logic_vector( GC_BYTES- 1 downto 0)
AXI-Stream data stream qualifier.
Definition nw_axis_source.vhd:83
GC_BYTES integer range 1 to 1024
Width of axis data in bytes.
Definition nw_axis_source.vhd:76
in pkt_len natural
Packet length (bytes)
Definition nw_axis_source.vhd:87
in pkt t_slv_arr
Packet to send (byte array)
Definition nw_axis_source.vhd:90
in aclk std_logic
AXI-Stream clock.
Definition nw_axis_source.vhd:78
in tready std_logic
AXI-Stream ready.
Definition nw_axis_source.vhd:80
out tdata std_logic_vector( GC_BYTES* 8- 1 downto 0)
AXI-Stream data.
Definition nw_axis_source.vhd:82
out done std_logic
Packet send done.
Definition nw_axis_source.vhd:86
in pkt_valid std_logic
Packet valid.
Definition nw_axis_source.vhd:88
out tlast std_logic
AXI-Stream last data.
Definition nw_axis_source.vhd:85
out tvalid std_logic
AXI-Stream data valid.
Definition nw_axis_source.vhd:81
in aresetn std_logic
AXI-Stream reset.
Definition nw_axis_source.vhd:79
out tstrb std_logic_vector( GC_BYTES- 1 downto 0)
AXI-Stream data byte qualifier.
Definition nw_axis_source.vhd:84

See further examples in the test bench nw_axis_tb.vhd.