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Network Wizard for VHDL Test Benches
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Functions | |
std_logic_vector | f_gen_crc ( poly: in std_logic_vector data: in t_slv_arr init: in std_logic_vector msb_first: in boolean C_MSB_FIRST ) |
std_logic_vector | f_gen_chksum ( data: in t_slv_arr chksum_width: in positive use_carry: in boolean True ) |