Network Wizard for VHDL Test Benches
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AXI-Stream sink

The AXI-Stream sink module will receive data packets on the bus. When tlast is asserted, marking the end of the packet, the pkt_valid signal is asserted for one clock cycle.

Instantiation template

i_axis_sink : entity nw_util.axis_sink
generic map (
GC_BYTES => 4,
)
port map (
aclk => aclk,
aresetn => aresetn,
tready => tready,
tvalid => tvalid,
tdata => tdata,
tkeep => tkeep,
tstrb => tstrb,
tlast => tlast,
pkt_len => pkt_len,
pkt_valid => pkt_valid,
pkt => pkt
);
Definition nw_axis_sink.vhd:73
GC_BYTES integer range 1 to 1024
Width of axis data in bytes.
Definition nw_axis_sink.vhd:75
GC_MAX_PKT_SIZE positive := 2000
Max paket size (bytes) to receive.
Definition nw_axis_sink.vhd:77
in aclk std_logic
AXI-Stream clock.
Definition nw_axis_sink.vhd:79
out pkt t_slv_arr( 0 to GC_MAX_PKT_SIZE- 1)( 7 downto 0) :=( others =>( others => '0'))
Packet received.
Definition nw_axis_sink.vhd:90
in tlast std_logic
AXI-Stream last data.
Definition nw_axis_sink.vhd:86
out pkt_valid std_logic := '0'
Packet valid strobe.
Definition nw_axis_sink.vhd:88
in tstrb std_logic_vector( GC_BYTES- 1 downto 0)
AXI-Stream data byte qualifier.
Definition nw_axis_sink.vhd:85
out pkt_len natural := 0
Packet length.
Definition nw_axis_sink.vhd:87
in tdata std_logic_vector( GC_BYTES* 8- 1 downto 0)
AXI-Stream data.
Definition nw_axis_sink.vhd:83
out tready std_logic
AXI-Stream ready.
Definition nw_axis_sink.vhd:81
in tvalid std_logic
AXI-Stream data valid.
Definition nw_axis_sink.vhd:82
in aresetn std_logic
AXI-Stream reset.
Definition nw_axis_sink.vhd:80
in tkeep std_logic_vector( GC_BYTES- 1 downto 0)
AXI-Stream data stream qualifier.
Definition nw_axis_sink.vhd:84

See further examples in the test bench nw_axis_tb.vhd.